(a) Field of the Invention
The present invention relates to a PDP (plasma display panel) driving method. More specifically, the present invention relates to a PDP driving method for stabilizing the sustain discharge.
(b) Description of the Related Art
A PDP is a flat display for displaying characters and images using plasma generated by gas discharge, and from several tens to several millions of pixels are provided in a matrix format on the PDP depending on the size of the pixels. A PDP may be classified as a direct current (DC) PDP or an alternating current (AC) PDP depending upon the patterns of the applied driving voltage waveforms and the structures of the discharge cells.
Electrodes of DC PDPs are exposed in the discharge space, and hence the current flows in the discharge space while the voltage is applied. Thus, a resistor must be provided for current restriction to solve this problem. Electrodes of AC PDPs are covered with a dielectric layer, and therefore the current is restricted because of formation of a natural capacitance component, and since the electrodes are protected from ion shocks at the discharge time, AC PDPs generally have a longer lifespan than DC PDPs.
FIG. 1 shows a partial perspective view of an AC PDP. As shown, pairs of scan electrodes 4 and sustain electrodes 5, which are covered with a dielectric layer 2 and a protection film 3, are provided in parallel below a first glass substrate 1. A plurality of address electrodes 8, which are covered with an insulation layer 7, are installed on a second glass substrate 6. Barrier ribs 9, which are parallel to the address electrodes 8, are formed on the insulation layer 7. Phosphor 10 is formed on the surface of the insulation layer 7 and on both sides of the barrier ribs 9.
The first glass substrate 1 and the second glass substrate 6 are provided facing each other with discharge areas 11 between them so the scan electrodes 4 and the sustain electrodes 5 may cross the address electrodes 8. The discharge area provided at crossing nodes of the address electrodes 8 and the pairs of the scan electrode 4 and the sustain electrode 5 form discharge cells 12.
FIG. 2 shows a PDP electrode arrangement diagram. As shown, the PDP electrode has an m×n matrix configuration, and in detail, address electrodes A1 through Am are arranged in the row direction, and n scan electrodes Y1 through Yn and n sustain electrodes X1 through Xn are alternately arranged in the column direction. The scan electrodes will be referred to as “Y electrodes,” and the sustain electrodes as “X electrodes” hereinafter. The discharge cell 12 of FIG. 2 corresponds to the discharge cell of FIG. 1.
FIG. 3 shows a conventional PDP driving waveform diagram. As shown, each subfield following a conventional PDP driving method comprises a reset period, an address period, and a sustain period. Eight to twelve subfields of the above-noted PDP form a single frame, and realize a single image.
During the reset period, a wall charge state of a previous sustain discharge is erased, and the wall charges are set up to stably perform the next addressing.
During the address period, cells to be turned on are selected to accumulate wall charges on the cells to be turned on (i.e., addressed cells). During the sustain period, a discharge is performed to display the actual images on the addressed cells.
FIGS. 4(a) through 4(d) show the wall charges distributed to the electrodes at the respective (a), (b), (c), and (d) periods of FIG. 3.
Referring to FIGS. 4(a) through 4(d), the operation of the conventional reset period will be described in detail. The reset period includes an erase period, a Y ramp rising period, and a Y ramp falling period.
(1) Erase Period
When the final sustain is finished, positive charges are accumulated to the X electrode, and negative charges are accumulated to the Y electrode, as shown in FIG. 4(a). The address voltage is maintained at 0V (volts) during the sustain period, however, because it tries to maintain a middle voltage of the sustain all the time, a relatively large amount of the positive charges are accumulated to the address electrodes.
When the sustain is finished, an erase ramp voltage that gradually increases from 0(V) to +Ve(V) is applied to the X electrode, and the wall charges formed on the X and Y electrodes are gradually erased, as shown in FIG. 4(b).
(2) Y Ramp Rising Period
During this period, the address electrode and the X electrode are maintained at 0V, and a ramp voltage is applied to the Y electrode, the ramp voltage gradually rising from the voltage Vs, which is below the discharge firing voltage with respect to the X electrode, to the voltage Vset, which is greater than the discharge firing voltage. While the ramp voltage rises, first weak resetting discharge is generated in all the discharge cells from the Y electrode to the address electrode and the X electrode. As a result, the negative wall charges are accumulated to the Y electrode, and concurrently, the positive wall charges are accumulated to the address electrode and the X electrode, as shown in FIG. 4(c).
(3) Y Ramp Falling Period
In the latter part of the reset period, a ramp voltage that gradually falls from the voltage Vs, which is below the discharge firing voltage, to 0(V) is applied to the Y electrode while the X electrode maintains a constant voltage Ve. While the ramp voltage falls, a second weak resetting discharge is generated in all the discharge cells because the potential difference between the X electrode and the Y electrode exceeds the discharge firing voltage. As a result, the negative wall charges of the Y electrode are reduced, and the polarity of the X electrode is inverted to accumulate weak negative charges thereto, as shown in FIG. 4(d). Also, the positive wall charges of the address electrode are adjusted to an appropriate value for the address operation. In this instance, when the reset operation is ideally performed, a voltage difference corresponding to the discharge firing voltage Vf is always maintained within the discharge cell as shown in Equation 1.Vf,xy=Ve+Vw,xy Vf,ay=Vw,ay  Equation 1where Vf,xy is a discharge firing voltage between the X and Y electrodes, Vf,ay is a discharge firing voltage between the address and Y electrodes, Vw,xy is a voltage caused by the wall charges accumulated to the X and Y electrodes, Vw,ay is a voltage caused by the wall charges accumulated to the address and Y electrodes, and Ve is an externally applied voltage between the X and Y electrodes.
As given by Equation 1, the discharge firing voltage can be maintained with a small amount of wall charge since the voltage Ve (substantially 200V) is supplied between the X and Y electrodes. However, the address electrodes and the Y electrodes are to maintain the discharge firing voltage using the wall charges since no external voltage is supplied to the address electrodes and the Y electrodes.
However, the charges shown in FIG. 4(d) with circles around them on the X and Y electrodes do not function to maintain the voltage difference between the X and Y electrodes. Nevertheless, these charges are accumulated because the discharge firing voltage between the address electrode and Y electrode is achieved using only the wall charges between the address and Y electrodes after accumulating a large amount of positive charges to the address electrode and a large amount of negative charges to the Y electrode.
FIG. 5 shows a detailed conventional waveform and a distribution of wall charges during the Y ramp falling period. The distribution diagram of the wall charges shown on the right of FIG. 5 shows a distribution of wall charges at the time (d). As shown, the X bias voltage Vx1 is easily discharged because it forms a relatively large potential difference. Further, since the background brightness increases, the entire contrast reduces. Also, the relative large X bias potential heavily erases the wall charges after the Y ramp rising, thereby generating unstable subsequent addressing.
FIG. 6 shows another conventional waveform and a distribution of wall charges in the Y ramp falling period.
As known from the waveform on the left of FIG. 6, an X bias voltage Vx2 which is relatively lower than the X bias voltage of FIG. 5 is applied to the sustain electrode.
In this case, however, discharge may be delayed since the potential between the Y electrode and the X electrode is low during the Y ramp falling period, and over-discharge is likely to occur because the large amount of the wall charges accumulated during the Y ramp rising period are not sufficiently erased.